linux-4.4.1/cpu_cache_fns
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開始行:
*参照元 [#ha94bcbe]
#backlinks
*説明 [#def2f3e8]
-パス: [[linux-4.4.1/arch/arm/include/asm/cacheflush.h]]
-FIXME: これは何?
--説明
**参考 [#y0f16536]
*実装 [#hfb13ac3]
/*
* MM Cache Management
* ===================
*
* The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*...
* implement these methods.
*
* Start addresses are inclusive and end addresses ...
* start addresses should be rounded down, end addr...
*
* See Documentation/cachetlb.txt for more informat...
* Please note that the implementation of these, an...
* effects are cache-type (VIVT/VIPT/PIPT) specific.
*
* flush_icache_all()
*
* Unconditionally clean and invalidate the...
* Currently only needed for cache-v6.S and...
* __flush_icache_all for the generic imple...
*
* flush_kern_all()
*
* Unconditionally clean and invalidate the...
*
* flush_kern_louis()
*
* Flush data cache levels up to the level o...
* inner shareable and invalidate the I-cache.
* Only needed from v7 onwards, falls back t...
* for all other processor versions.
*
* flush_user_all()
*
* Clean and invalidate all user space cach...
* before a change of page tables.
*
* flush_user_range(start, end, flags)
*
* Clean and invalidate a range of cache en...
* specified address space before a change ...
* - start - user start address (inclusive,...
* - end - user end address (exclusive,...
* - flags - vma->vm_flags field
*
* coherent_kern_range(start, end)
*
* Ensure coherency between the Icache and ...
* region described by start, end. If you ...
* Harvard caches, you need to implement th...
* - start - virtual start address
* - end - virtual end address
*
* coherent_user_range(start, end)
*
* Ensure coherency between the Icache and ...
* region described by start, end. If you ...
* Harvard caches, you need to implement th...
* - start - virtual start address
* - end - virtual end address
*
* flush_kern_dcache_area(kaddr, size)
*
* Ensure that the data held in page is wri...
* - kaddr - page address
* - size - region size
*
* DMA Cache Coherency
* ===================
*
* dma_flush_range(start, end)
*
* Clean and invalidate the specified virtu...
* - start - virtual start address
* - end - virtual end address
*/
struct cpu_cache_fns {
void (*flush_icache_all)(void);
void (*flush_kern_all)(void);
void (*flush_kern_louis)(void);
void (*flush_user_all)(void);
void (*flush_user_range)(unsigned long, unsigned...
void (*coherent_kern_range)(unsigned long, unsig...
int (*coherent_user_range)(unsigned long, unsig...
void (*flush_kern_dcache_area)(void *, size_t);
void (*dma_map_area)(const void *, size_t, int);
void (*dma_unmap_area)(const void *, size_t, int);
void (*dma_flush_range)(const void *, const void...
};
*コメント [#yaf13972]
終了行:
*参照元 [#ha94bcbe]
#backlinks
*説明 [#def2f3e8]
-パス: [[linux-4.4.1/arch/arm/include/asm/cacheflush.h]]
-FIXME: これは何?
--説明
**参考 [#y0f16536]
*実装 [#hfb13ac3]
/*
* MM Cache Management
* ===================
*
* The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*...
* implement these methods.
*
* Start addresses are inclusive and end addresses ...
* start addresses should be rounded down, end addr...
*
* See Documentation/cachetlb.txt for more informat...
* Please note that the implementation of these, an...
* effects are cache-type (VIVT/VIPT/PIPT) specific.
*
* flush_icache_all()
*
* Unconditionally clean and invalidate the...
* Currently only needed for cache-v6.S and...
* __flush_icache_all for the generic imple...
*
* flush_kern_all()
*
* Unconditionally clean and invalidate the...
*
* flush_kern_louis()
*
* Flush data cache levels up to the level o...
* inner shareable and invalidate the I-cache.
* Only needed from v7 onwards, falls back t...
* for all other processor versions.
*
* flush_user_all()
*
* Clean and invalidate all user space cach...
* before a change of page tables.
*
* flush_user_range(start, end, flags)
*
* Clean and invalidate a range of cache en...
* specified address space before a change ...
* - start - user start address (inclusive,...
* - end - user end address (exclusive,...
* - flags - vma->vm_flags field
*
* coherent_kern_range(start, end)
*
* Ensure coherency between the Icache and ...
* region described by start, end. If you ...
* Harvard caches, you need to implement th...
* - start - virtual start address
* - end - virtual end address
*
* coherent_user_range(start, end)
*
* Ensure coherency between the Icache and ...
* region described by start, end. If you ...
* Harvard caches, you need to implement th...
* - start - virtual start address
* - end - virtual end address
*
* flush_kern_dcache_area(kaddr, size)
*
* Ensure that the data held in page is wri...
* - kaddr - page address
* - size - region size
*
* DMA Cache Coherency
* ===================
*
* dma_flush_range(start, end)
*
* Clean and invalidate the specified virtu...
* - start - virtual start address
* - end - virtual end address
*/
struct cpu_cache_fns {
void (*flush_icache_all)(void);
void (*flush_kern_all)(void);
void (*flush_kern_louis)(void);
void (*flush_user_all)(void);
void (*flush_user_range)(unsigned long, unsigned...
void (*coherent_kern_range)(unsigned long, unsig...
int (*coherent_user_range)(unsigned long, unsig...
void (*flush_kern_dcache_area)(void *, size_t);
void (*dma_map_area)(const void *, size_t, int);
void (*dma_unmap_area)(const void *, size_t, int);
void (*dma_flush_range)(const void *, const void...
};
*コメント [#yaf13972]
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