linux-4.4.1/NMRR
をテンプレートにして作成
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開始行:
*参照元 [#jdcc7586]
#backlinks
*説明 [#b291b8c1]
-パス: 複数あり
--CONFIG_ARM_LPAE 無効: [[linux-4.4.1/arch/arm/mm/proc-v7...
--CONFIG_ARM_LPAE 有効: [[linux-4.4.1/arch/arm/mm/proc-v7...
--[[linux-4.4.1/CONFIG_ARM_LPAE]]
-FIXME: これは何？
--Normal Memory Remap Register (ARMv7, CP15, CRn=c10, opc...
--PRRR と一緒に使う
---[[linux-4.4.1/PRRR]]
**参考 [#h191c11b]
*実装 [#n952ab75]
**CONFIG_ARM_LPAE 無効: arch/arm/mm/proc-v7-2level.S [#r5...
/*
* Memory region attributes with SCTLR.TRE=1
*
* n = TEX[0],C,B
* TR = PRRR[2n+1:2n] - memory type
* IR = NMRR[2n+1:2n] - inner cacheabl...
* OR = NMRR[2n+17:2n+16] - outer cacheabl...
*
* n TR IR OR
* UNCACHED 000 00
* BUFFERABLE 001 10 00 00
* WRITETHROUGH 010 10 10 10
* WRITEBACK 011 10 11 11
* reserved 110
* WRITEALLOC 111 10 01 01
* DEV_SHARED 100 01
* DEV_NONSHARED 100 01
* DEV_WC 001 10
* DEV_CACHED 011 10
*
* Other attributes:
*
* DS0 = PRRR[16] = 0 - device shareab...
* DS1 = PRRR[17] = 1 - device shareab...
* NS0 = PRRR[18] = 0 - normal shareab...
* NS1 = PRRR[19] = 1 - normal shareab...
* NOS = PRRR[24+n] = 1 - not outer shar...
*/
...
.equ NMRR, 0x40e040e0
**CONFIG_ARM_LPAE 有効: arch/arm/mm/proc-v7-3level.S [#q9...
/*
* Memory region attributes for LPAE (defined in...
*
* n = AttrIndx[2:0]
*
* n MAIR
* UNCACHED 000 00000000
* BUFFERABLE 001 01000100
* DEV_WC 001 01000100
* WRITETHROUGH 010 10101010
* WRITEBACK 011 11101110
* DEV_CACHED 011 11101110
* DEV_SHARED 100 00000100
* DEV_NONSHARED 100 00000100
* unused 101
* unused 110
* WRITEALLOC 111 11111111
*/
...
.equ NMRR, 0xff000004 @ MAIR1
*コメント [#o8a5f653]
終了行:
*参照元 [#jdcc7586]
#backlinks
*説明 [#b291b8c1]
-パス: 複数あり
--CONFIG_ARM_LPAE 無効: [[linux-4.4.1/arch/arm/mm/proc-v7...
--CONFIG_ARM_LPAE 有効: [[linux-4.4.1/arch/arm/mm/proc-v7...
--[[linux-4.4.1/CONFIG_ARM_LPAE]]
-FIXME: これは何？
--Normal Memory Remap Register (ARMv7, CP15, CRn=c10, opc...
--PRRR と一緒に使う
---[[linux-4.4.1/PRRR]]
**参考 [#h191c11b]
*実装 [#n952ab75]
**CONFIG_ARM_LPAE 無効: arch/arm/mm/proc-v7-2level.S [#r5...
/*
* Memory region attributes with SCTLR.TRE=1
*
* n = TEX[0],C,B
* TR = PRRR[2n+1:2n] - memory type
* IR = NMRR[2n+1:2n] - inner cacheabl...
* OR = NMRR[2n+17:2n+16] - outer cacheabl...
*
* n TR IR OR
* UNCACHED 000 00
* BUFFERABLE 001 10 00 00
* WRITETHROUGH 010 10 10 10
* WRITEBACK 011 10 11 11
* reserved 110
* WRITEALLOC 111 10 01 01
* DEV_SHARED 100 01
* DEV_NONSHARED 100 01
* DEV_WC 001 10
* DEV_CACHED 011 10
*
* Other attributes:
*
* DS0 = PRRR[16] = 0 - device shareab...
* DS1 = PRRR[17] = 1 - device shareab...
* NS0 = PRRR[18] = 0 - normal shareab...
* NS1 = PRRR[19] = 1 - normal shareab...
* NOS = PRRR[24+n] = 1 - not outer shar...
*/
...
.equ NMRR, 0x40e040e0
**CONFIG_ARM_LPAE 有効: arch/arm/mm/proc-v7-3level.S [#q9...
/*
* Memory region attributes for LPAE (defined in...
*
* n = AttrIndx[2:0]
*
* n MAIR
* UNCACHED 000 00000000
* BUFFERABLE 001 01000100
* DEV_WC 001 01000100
* WRITETHROUGH 010 10101010
* WRITEBACK 011 11101110
* DEV_CACHED 011 11101110
* DEV_SHARED 100 00000100
* DEV_NONSHARED 100 00000100
* unused 101
* unused 110
* WRITEALLOC 111 11111111
*/
...
.equ NMRR, 0xff000004 @ MAIR1
*コメント [#o8a5f653]
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