*参照元 [#ha94bcbe] #backlinks *説明 [#def2f3e8] -パス: [[linux-4.4.1/arch/arm/include/asm/cacheflush.h]] -FIXME: これは何? --説明 **参考 [#y0f16536] *実装 [#hfb13ac3] /* * MM Cache Management * =================== * * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files * implement these methods. * * Start addresses are inclusive and end addresses are exclusive; * start addresses should be rounded down, end addresses up. * * See Documentation/cachetlb.txt for more information. * Please note that the implementation of these, and the required * effects are cache-type (VIVT/VIPT/PIPT) specific. * * flush_icache_all() * * Unconditionally clean and invalidate the entire icache. * Currently only needed for cache-v6.S and cache-v7.S, see * __flush_icache_all for the generic implementation. * * flush_kern_all() * * Unconditionally clean and invalidate the entire cache. * * flush_kern_louis() * * Flush data cache levels up to the level of unification * inner shareable and invalidate the I-cache. * Only needed from v7 onwards, falls back to flush_cache_all() * for all other processor versions. * * flush_user_all() * * Clean and invalidate all user space cache entries * before a change of page tables. * * flush_user_range(start, end, flags) * * Clean and invalidate a range of cache entries in the * specified address space before a change of page tables. * - start - user start address (inclusive, page aligned) * - end - user end address (exclusive, page aligned) * - flags - vma->vm_flags field * * coherent_kern_range(start, end) * * Ensure coherency between the Icache and the Dcache in the * region described by start, end. If you have non-snooping * Harvard caches, you need to implement this function. * - start - virtual start address * - end - virtual end address * * coherent_user_range(start, end) * * Ensure coherency between the Icache and the Dcache in the * region described by start, end. If you have non-snooping * Harvard caches, you need to implement this function. * - start - virtual start address * - end - virtual end address * * flush_kern_dcache_area(kaddr, size) * * Ensure that the data held in page is written back. * - kaddr - page address * - size - region size * * DMA Cache Coherency * =================== * * dma_flush_range(start, end) * * Clean and invalidate the specified virtual address range. * - start - virtual start address * - end - virtual end address */ struct cpu_cache_fns { void (*flush_icache_all)(void); void (*flush_kern_all)(void); void (*flush_kern_louis)(void); void (*flush_user_all)(void); void (*flush_user_range)(unsigned long, unsigned long, unsigned int); void (*coherent_kern_range)(unsigned long, unsigned long); int (*coherent_user_range)(unsigned long, unsigned long); void (*flush_kern_dcache_area)(void *, size_t); void (*dma_map_area)(const void *, size_t, int); void (*dma_unmap_area)(const void *, size_t, int); void (*dma_flush_range)(const void *, const void *); }; *コメント [#yaf13972]