*参照元 [#z909d4f3] #backlinks *説明 [#r33c3c73] -パス: 複数あり --CONFIG_ARM_LPAE 無効: [[linux-4.4.1/arch/arm/mm/proc-v7-2level.S]] --CONFIG_ARM_LPAE 有効: [[linux-4.4.1/arch/arm/mm/proc-v7-3level.S]] -FIXME: これは何? --Primary Region Remap Register (ARMv7, CP15, CRn=c10, opc1=0, CRm=c2, opc2=0) --NMRR と一緒に使う ---[[linux-4.4.1/NMRR]] **参考 [#od7481f1] *実装 [#pc6e56a9] **CONFIG_ARM_LPAE 無効: arch/arm/mm/proc-v7-2level.S [#pbd15500] /* * Memory region attributes with SCTLR.TRE=1 * * n = TEX[0],C,B * TR = PRRR[2n+1:2n] - memory type * IR = NMRR[2n+1:2n] - inner cacheable property * OR = NMRR[2n+17:2n+16] - outer cacheable property * * n TR IR OR * UNCACHED 000 00 * BUFFERABLE 001 10 00 00 * WRITETHROUGH 010 10 10 10 * WRITEBACK 011 10 11 11 * reserved 110 * WRITEALLOC 111 10 01 01 * DEV_SHARED 100 01 * DEV_NONSHARED 100 01 * DEV_WC 001 10 * DEV_CACHED 011 10 * * Other attributes: * * DS0 = PRRR[16] = 0 - device shareable property * DS1 = PRRR[17] = 1 - device shareable property * NS0 = PRRR[18] = 0 - normal shareable property * NS1 = PRRR[19] = 1 - normal shareable property * NOS = PRRR[24+n] = 1 - not outer shareable */ ... .equ PRRR, 0xff0a81a8 **CONFIG_ARM_LPAE 有効: arch/arm/mm/proc-v7-3level.S [#seb0a32e] /* * Memory region attributes for LPAE (defined in pgtable-3level.h): * * n = AttrIndx[2:0] * * n MAIR * UNCACHED 000 00000000 * BUFFERABLE 001 01000100 * DEV_WC 001 01000100 * WRITETHROUGH 010 10101010 * WRITEBACK 011 11101110 * DEV_CACHED 011 11101110 * DEV_SHARED 100 00000100 * DEV_NONSHARED 100 00000100 * unused 101 * unused 110 * WRITEALLOC 111 11111111 */ ... .equ PRRR, 0xeeaa4400 @ MAIR0 *コメント [#iac5af0e]