*参照元 [#k629ed1a]
#backlinks

*説明 [#w3d46434]
-パス: [[linux-2.6.33/]]

-FIXME: これは何?
--説明


**引数 [#za57385c]
-
--

**返り値 [#o4dd2b7a]
-
--

**参考 [#i0c9b2bf]


*実装 [#cb463f30]
 /*
  * Vector stubs.
  *
  * This code is copied to 0xffff0200 so we can use branches in the
  * vectors, rather than ldr's.  Note that this code must not
  * exceed 0x300 bytes.
  *
  * Common stub entry macro:
  *   Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
  *
  * SP points to a minimal amount of processor-private memory, the address
  * of which is copied into r0 for the mode specific abort handler.
  */
 	.macro	vector_stub, name, mode, correction=0
 	.align	5
 
 vector_\name:
 	.if \correction
 	sub	lr, lr, #\correction
 	.endif
 
 	@
 	@ Save r0, lr_<exception> (parent PC) and spsr_<exception>
 	@ (parent CPSR)
 	@
 	stmia	sp, {r0, lr}		@ save r0, lr
 	mrs	lr, spsr
 	str	lr, [sp, #8]		@ save spsr
 
 	@
 	@ Prepare for SVC32 mode.  IRQs remain disabled.
 	@
 	mrs	r0, cpsr
 	eor	r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
 	msr	spsr_cxsf, r0
 
 	@
 	@ the branch table must immediately follow this code
 	@
 	and	lr, lr, #0x0f
  THUMB(	adr	r0, 1f			)
  THUMB(	ldr	lr, [r0, lr, lsl #2]	)
 	mov	r0, sp
  ARM(	ldr	lr, [pc, lr, lsl #2]	)
 	movs	pc, lr			@ branch to handler in SVC mode
 ENDPROC(vector_\name)
 
 	.align	2
 	@ handler addresses follow this label
 1:
 	.endm


*コメント [#nfcdaef6]

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